In high-speed PCB design, multi-layer PCBs are often required, and vias are an important factor in multi-layer PCB design. The via hole in the PCB is mainly composed of three parts: the hole, the pad area around the hole, and the POWER layer isolation area.
Impact of vias in high-speed PCBs
In a high-speed PCB multilayer board, the signal needs to be connected through a via hole when it is transmitted from a certain layer of interconnection wires to another layer of interconnection wires. When the frequency is lower than 1 GHz, the via hole can play a very good connection role. , its parasitic capacitance and inductance can be ignored. When the frequency is higher than 1 GHz, the influence of via parasitics on signal integrity cannot be ignored. At this time, vias appear as discontinuous impedance breakpoints on the transmission path, which will cause signal reflection, delay, and attenuation. and other signal integrity issues. When the signal is transmitted to another layer through the via, the reference layer of the signal line also serves as the return path of the via signal, and the return current will flow between the reference layers through capacitive coupling, causing problems such as ground bounce.
Via Type
Vias are generally divided into three categories: through holes, blind holes and buried holes.
Blind holes refer to the top and bottom surfaces of the printed circuit board, with a certain depth, and are used to connect the surface circuit and the inner layer circuit below. The depth and diameter of the hole usually do not exceed a certain ratio.
Buried hole refers to the connection hole located in the inner layer of the printed circuit board, which does not extend to the surface of the circuit board.
Through holes, which pass through the entire circuit board, can be used for internal interconnection or as mounting positioning holes for components. Since the through hole is easier to realize in the process and the cost is lower, it is generally used in printed circuit boards.
Via Design in High Speed PCB
In high-speed PCB design, seemingly simple vias often bring great negative effects to circuit design. In order to reduce the adverse effects brought by the parasitic effects of vias, we can try our best in the design:
(1) Choose a reasonable via size. For multi-layer PCB design with general density, it is better to use 0.25mm/0.51mm/0.91mm (drilling hole/pad/POWER isolation area) via hole; for some high-density PCBs, 0.20mm/0.46mm can also be used mm/0.86mm via holes, you can also try non-piercing holes; for power or ground via holes, you can consider using a larger size to reduce impedance;
(2) The larger the POWER isolation area, the better, considering the via density on the PCB, generally D1=D2+0.41;
(3) The signal traces on the PCB should not change layers as much as possible, that is to say, minimize vias;
(4) Using a thinner PCB is beneficial to reduce the two parasitic parameters of the via;
(5) The pins of the power supply and the ground should be via holes nearby, and the shorter the leads between the via holes and the pins, the better, because they will lead to an increase in inductance. At the same time, the leads of power supply and ground should be as thick as possible to reduce impedance;
(6) Place some ground vias near the vias where the signal changes layers to provide a short-distance loop for the signal.
In addition, the length of the via is also one of the main factors affecting the inductance of the via. For vias used for top and bottom conduction, the length of the via is equal to the thickness of the PCB. Due to the continuous increase in the number of PCB layers, the thickness of the PCB often reaches more than 5 mm. However, in high-speed PCB design, in order to reduce the problems caused by vias, the length of vias is generally controlled within 2.0mm. For vias with a via length greater than 2.0 mm, the via impedance continuity can be improved to a certain extent by increasing the via hole diameter. When the via length is 1.0 mm or less, the optimum via diameter is 0.20 mm to 0.30 mm.